1. Field of the Invention
Generally, the present disclosure relates to the formation of microstructures, such as advanced integrated circuits, and, more particularly, to the formation and examination of conductive structures, such as metal regions, and their characteristics during stress conditions.
2. Description of the Related Art
In the fabrication of modern microstructures, such as integrated circuits, there is a continuous drive to steadily reduce the feature sizes of microstructure elements, thereby enhancing the functionality of these structures. For instance, in modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep submicron range, thereby increasing performance of these circuits in terms of speed and/or power consumption. As the size of individual circuit elements is reduced with every new circuit generation, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these inter-connect lines have to be reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit die area. The reduced cross-sectional area of the interconnect lines, possibly in combination with an increase in the static power consumption of extremely scaled transistor elements, may require a plurality of stacked metallization layers to meet the requirements in view of a tolerable current density in the metal lines.
Advanced integrated circuits, including transistor elements having a critical dimension of 0.13 μm and even less, may, however, require significantly increased current densities in the individual interconnect lines, despite the provision of a relatively large number of metallization layers, owing to the significant number of circuit elements per unit area. Operating the interconnect lines at elevated current densities, however, may entail a plurality of problems related to stress-induced line degradation, which may finally lead to a premature failure of the integrated circuit. One prominent phenomenon in this respect is the current-induced material transportation in metal regions, i.e., lines and vias, also referred to as “electromigration,” which may lead to the formation of voids within and hillocks or protrusions next to the metal regions, thereby resulting in reduced performance and reliability or complete failure of the device. For instance, aluminum lines and vias embedded into silicon dioxide and/or silicon nitride are frequently used as metal for metallization layers, wherein, as explained above, advanced integrated circuits having critical dimensions of 0.18 μm or less, may require significantly reduced cross-sectional areas of the metal lines and, thus, increased current densities, which may render aluminum less attractive for the formation of metallization layers.
Consequently, aluminum is increasingly being replaced by copper as copper exhibits a significantly lower resistivity and exhibits significant electromigration effects at considerably higher current densities as compared to aluminum. The introduction of copper into the fabrication of microstructures and integrated circuits comes along with a plurality of severe problems residing in copper's characteristic to readily diffuse in silicon dioxide and a plurality of low-k dielectric materials. To provide the necessary adhesion and to avoid the undesired diffusion of copper atoms into sensitive device regions, it is, therefore, usually necessary to provide a barrier layer between the copper and the dielectric material in which the copper lines and vias are embedded. Although silicon nitride is a dielectric material that effectively prevents the diffusion of copper atoms, selecting silicon nitride as an interlayer dielectric material is less then desirable, since silicon nitride exhibits a moderately high permittivity, thereby increasing the parasitic capacitance of neighboring copper lines. Hence, a thin conductive barrier layer that also imparts the required mechanical stability to the copper is formed to separate the bulk copper from the surrounding dielectric material, and only a thin silicon nitride or silicon carbide or silicon carbon nitride layer in the form of a capping layer is frequently used in copper-based metallization layers. Currently, tantalum, titanium, tungsten, tungsten/cobalt/phosphorous compounds, tungsten/cobalt/boron compounds and their compounds with nitrogen and silicon and the like are preferred candidates for a conductive barrier layer, wherein the barrier layer may comprise two or more sub-layers of different composition to meet the requirements in terms of diffusion suppressing and adhesion properties.
Another characteristic of copper significantly distinguishing it from aluminum is the fact that copper may not be readily deposited in large amounts by chemical and physical vapor deposition techniques. Additionally, copper may not be efficiently patterned by anisotropic dry etch processes, thereby requiring a process strategy that is commonly referred to as the damascene or inlaid technique. In the damascene process, first a dielectric layer is formed which is then patterned to include trenches and vias which are subsequently filled with copper or copper alloys, wherein, as previously noted, prior to filling in the copper-based metal, a conductive barrier layer is formed within the trenches and vias. The deposition of the bulk copper material into the trenches and vias is usually accomplished by wet chemical deposition processes, such as electroplating and electroless plating, thereby requiring the reliable filling of vias with an aspect ratio of 5 and more with a diameter of 0.1 μm or even less in combination with trenches having a width ranging from 0.1 μm or less to several μm. Although electrochemical deposition processes for copper are well established in the field of electronic circuit board fabrication, a substantially void-free filling of high aspect ratio vias is an extremely complex and challenging task, wherein the characteristics of the finally obtained copper metal line depend significantly on process parameters, materials and geometry of the structure of interest. Since the dimensions of interconnect structures are determined by the design requirements and may, therefore, not be significantly altered for a given microstructure, it is of great importance to estimate and control the impact of materials, such as conductive and non-conductive barrier layers, of the copper-based microstructure and their mutual interaction on the characteristics of the interconnect structure so as to insure both high yield and the required product reliability. In particular, it is important to identify and monitor degradation and failure mechanisms in interconnect structures for various configurations to maintain device reliability for every new device generation or technology node.
Accordingly, a great deal of effort has been made in the past decades in investigating the degradation of copper lines and vias, especially in view of electromigration, in order to find new materials and process strategies for forming copper-based metal lines and vias. Although the exact mechanism of electromigration in copper lines and vias is still not quite fully understood, it turns out that voids positioned in and on sidewalls and interfaces and voids and residuals at the via bottom may have a significant impact on production yield and reliability. Except for gross failures, such defects in vias, which may be provided in the form of via chains as control monitor structures in wafer scribe lines, are difficult to detect in standard electrical testing procedures. Thus, great efforts are made in designing appropriately configured test structures in order to estimate the electromigration behavior of vias and lines to estimate the expected time to failure for vias and metal lines, wherein the results may be indicative for the specifics of actual metallization structures only when well-defined conditions may be established in the test structure. Otherwise, the respective test results may lead to substantially meaningless statements with respect to the actual circuit features. For example, for estimating the mean time to failure of a via and a line connected thereto, which are manufactured according to a specific process flow on the basis of specified materials, such as copper, aluminum, silver and the like, including specific barrier materials, a test structure is formed on the basis of the specific process flow, wherein the design of the test structure is selected such that an electromigration induced failure, i.e., a respective flux divergence of the material flux in the line or via, is caused in a specified section of the test structure only. Thus, by applying well-defined stress conditions, such as temperature and an injected current, the respective section may be monitored with respect to a resistance increase that may indicate an electromigration induced void formation and thus a line or via failure.
With reference to FIGS. 1a-1c, a typical conventional test structure for estimating electromigration effects in metallization layers of semiconductor devices will now be described in more detail in order to demonstrate the principles and the problems associated with the conventional test regime.
FIG. 1a schematically illustrates a cross-sectional view of a portion of a test structure 100 comprising a substrate 101, which may represent any appropriate substrate for forming semiconductor devices or any other microstructural features which require a metallization layer for providing electrical connections in accordance with a specific circuit layout. For instance, the substrate 101 may represent a semiconductor substrate, such as a silicon substrate, having formed thereon a respective semiconductor layer suitable for the formation of circuit elements, such as transistors, capacitors and the like. A first dielectric layer 102, which may be comprised of any appropriate dielectric material as may be used in the metallization layer under consideration, is formed above the substrate 101 and may represent the dielectric material of a respective metallization layer. For instance, the dielectric layer 102 may be formed on the basis of the same process techniques and materials as are used for metallization layers in other substrates or the layer 102 may represent a portion of a metallization layer of a semiconductor device including the test structure 100 at a specific substrate location. Moreover, a metal line 103 may be formed within the dielectric layer 102 and may have specified dimensions and characteristics so as to exhibit a reduced probability for suffering from electromigration effects, that is, metal diffusion when subjected to predefined test conditions. The metal line 103 may be confined by a conductive barrier layer 104, comprised of, for instance, tantalum and the like, and a dielectric cap layer 109 that may be comprised of any appropriate material, such as silicon nitride and the like. Furthermore, respective metal lines 106 are provided in a next metallization level comprising a further dielectric layer 108 including a cap layer 110, wherein the metal lines 106 are connected to the metal line 103 by respective vias 105. Similar to the metal line 103, the lines 106 and the vias may also include a conductive barrier layer 107.
The test structure 100 may represent a test structure for evaluating the reliability of the metallization level comprising the metal lines 106 and the vias 105. As previously explained, electromigration effects have been the subject of extensive investigations over several decades, wherein it was recognized that electromigration, originating from the interaction of the moving electrons with diffusing metal atoms, thereby exerting a net force on the diffusing metal atoms at high charge carrier densities, may be one dominant reason for premature device failure, thus requiring efficient mechanisms for identifying and avoiding or reducing metal line and via degradation mechanisms. Since electromigration is an interaction between electrons and diffusing metal atoms, such as increased diffusion activity, for instance due to increased temperature, an increased degree of lattice defects, or in general due to the presence of increased diffusion paths, such as grain boundaries, respective interfaces and the like, electromigration is highly dependent on the specific manufacturing techniques and materials used. In advanced semiconductor devices, the dimensions of the respective vias and metal lines may also have a significant influence on the finally achieved degree of material transport within the metal lines. Although, in modern semiconductor devices, copper and copper alloys are frequently used which exhibit a significantly higher resistance against electromigration and have a lower electrical resistance, the ongoing reduction in line width has resulted in moderately high current densities, also causing a high degree of electromigration in copper-based metallization layers. Since a plurality of complex mechanisms may have a significant influence on the electromigration behavior, such as grain size, grain orientation, type of barrier material used, type of dielectric barrier materials and the like, it is of great importance to effectively monitor manufacturing techniques in order to control and improve product reliability. Thus, specifically designed test structures, such as the structure 100, have been developed, which may enable obtaining meaningful estimations on the electromigration characteristics.
When the characteristics of the lines and vias 106, 105 are to be examined, the metal line 103 is typically configured such that, with respect to the respective electromigration conditions, a corresponding material transport may substantially not occur. For this purpose, in conventional techniques, the line 103 may have a significantly reduced length compared to the lines 106, which are typically formed on the basis of design rules of actual devices.
FIG. 1b schematically illustrates a top view of the test structure 100 as shown in FIG. 1a, wherein voltage taps 111 are shown which are connected to the line 106, which may be considered as a device under test (DUT). Hence, the voltage taps 111 enable obtaining measurement values with respect to resistance degradation of the line 106 during an electromigration test.
FIG. 1c schematically illustrates a top view of the structure 100 according to a space-efficient implementation, wherein a plurality of lines 106 are connected by means of the vias 105 and respective short metal lines 103. The test chain of the structure 100 allows enhanced measurement accuracy and statistical significance, due to the plurality of metal lines 106 involved, wherein the measurement data may be obtained by appropriately positioned voltage taps, such as the taps 111.
The test structure 100 may be formed on the basis of well-established techniques, using the inlaid or damascene technique, wherein, as previously explained, the conductive barrier layer 107 is provided in order to obtain the required characteristics with respect to the suppression of diffusion of copper into the dielectric material and diffusion of reactive components into the copper-based metal regions, wherein, additionally, the characteristics of the barrier layer 107 may significantly affect the electromigration behavior.
During operation of the test structure 100, a respective current may be injected into the lines 106 in order to create an electron flow from one of the lines 106 to another line 106 via the metal line 103 and the vias 105. By means of the voltage taps 111, a respective resistance increase may be detected which indicates a corresponding void formation in the via 105 and/or the metal line 106, since these components are expected to be the “weakest” members of the entire conductive path. Consequently, the resistance change may be used as an indication for the electromigration behavior of the interconnect system including the via 105 and the metal line 106. For example, respective mean times to failure may be estimated on the basis of the resistance measurements. In practice, the corresponding time to failure and, thus, the reliability metrics derived from the test structure 100 may, in some cases, lead to unrealistic predictions for actual devices, especially for extremely scaled metallization structures involving the formation of respective barrier layers. For example, the corresponding barrier layer 107 may have been formed with reduced thickness or coverage at the bottom of one or more of the vias 105 due to process related non-uniformities during the physical vapor deposition, as is typically used for applying the barrier layer 107. Due to the non-uniformity of the barrier layer 107 at the via bottom, a significant mass flow may also occur in the metal line 103 during the stress test, thereby acting as a reservoir of copper for the metal line 106 located downstream of the metal line 103, representing the device under consideration. Hence, a regular void formation, corresponding to the electromigration conditions presently established, in the metal line 106 under consideration may be significantly reduced due to the replenishment of lost copper by the mass flow through the line 103, which is usually expected to lack a significant mass flow. As a consequence, based on the electromigration test, the line 106 under consideration may indicate a long life time and thus reliability of the respective actual metallization structures, while, however, the test structure 100 itself may be faulty, thereby rendering the measurement results of the test structure 100 less reliable.
The present disclosure is directed to various methods and systems that may avoid, or at least reduce, the effects of one or more of the problems identified above.